The operation of an instruction buffer is to transfer instructions from a computer memory to an instruction decoder. As is known in the prior art, a computer memory may store a block of instructions. Segments of the block of instructions are transferred to a cache memory, as needed, and the cache memory in turn sequentially transfers the instructions to the instruction buffer.
The instruction buffer buffers the instructions from the cache memory to the instruction decoder. In this way, the cache memory is allowed operational versatility in that it does not have to perform hand-shaking operations with the instruction decoder. For example, the cache memory may be ready to send four instructions to the instruction decoder, but the instruction decoder may not be ready to receive the four instructions. The instruction buffer takes the instructions from the cache memory and holds the instructions for the instruction decoder until the instruction decoder is ready to receive the instructions.
FIG. 1 shows a conventional instruction buffer configuration wherein instructions are fed, one at a time, from a memory 101 to instruction buffer 103 (or, alternatively, directly to the four-to-one multiplexer 109). With each cycle, instruction buffer 103 may receive one instruction from memory 101, and address buffer 104 may receive the corresponding address. If instruction buffer 103 already has an instruction before it is to receive a second instruction from memory 101, then that first instruction is fed to instruction buffer 105 (and the corresponding address in address buffer 104 is fed to address buffer 106), before instruction buffer 103 and address buffer 104 receive the second instruction and address from memory 101.
In the same way that the first instruction is shifted down from instruction buffer 103 upon receipt of a second instruction, a third instruction fed to instruction buffer 103 may cause the second instruction to shift to instruction buffer 105 and the first instruction to shift to instruction buffer 107.
Instruction buffer 107 is connected at its output to the four-to-one multiplexer 109, as are instruction buffers 103 and 105 at their respective outputs. Line 102 connects memory 101 directly to the four-to-one multiplexer 109, such that instructions may by-pass the three instruction buffers 103, 105, and 107 altogether. When the three instruction buffers are not by-passed with line 102, the four-to-one multiplexer 109 sequentially selects instructions from the three instruction buffers 103, 105, and 107 in the same order as they were fed from memory 101. The four-to-one multiplexer 109 outputs instructions to instruction decoder 111, one at a time.
The configuration of FIG. 1 has several drawbacks. For instance, the system is only able to provide a single instruction to instruction decoder 111 for any given cycle. Also, the speed of the system is severely limited because of the bottleneck created at the memory 101 and instruction buffer 103 interface. That is, when the three instruction buffers are not by-passed, memory 101 can only feed instructions to the instruction buffer configuration as fast as instruction buffer 103 can accept the instructions which is at a speed of one instruction per cycle.